The present invention relates to an error correction apparatus for use in digital transmission systems, and in particular to a high-speed error correction apparatus for decoding received convolutional code bits using the Viterbi decoding algorithm.
Recent advances in digital techniques in telecommunication have brought about numerous proposals and new systems for correcting errors introduced in transmission facilities, particularly satellite communications. The Viterbi decoding algorithm has been employed in these proposed systems and highly evaluated because its practical utility. The Viterbi decoding algorithm involves iterative operations of sequential selection of one of two metric paths that remerge at a node in the decoder's trellis diagram by detecting the greater of accumulated metric values so that the selected path is taken as one having a maximum likelihood. Prior art error correction apparatus using the Viterbi decoding algorithm repeats the operations of add, compare and select on each time slot which corresponds to the period of a single bit or a single code word. However, the time taken to effect the add operation imposes limitations on the operating speed of the system, making it unsuitable for high speed data processing. With the current CMOS integrated circuit technology the maximum operating speed does not exceeds 10 Mb/sec.